The present invention relates generally to a computer implemented method and system for emulating a design and in particular to emulating a design using a multitude of FPGAs with faster emulation implementation when the design is changed.
A field programmable gate array provides a multitude of programmable logic circuits that may be configured to emulate a circuit design, hereinafter also referred to as “design under test (DUT)”, at higher speed than computer based simulation. Emulation thus provides a way to validate the interface of a circuit design with hardware peripherals such as through a universal serial bus (USB) emulated on the FPGA that may be difficult to test using slower running computer simulation. A compiler software program translates a DUT's representation, such as hardware description language (HDL), netlist, or other description into one or more bitstreams, which may then be loaded into one or more FPGAs to configure the FPGAs to emulate the circuit. The FPGAs may then emulate the logic functions of the DUT in logic circuits on the FPGAs.
For complex circuit designs, the compiler software typically partitions the DUT into a multitude of FPGAs on a printed circuit board, which includes wiring or nets that provide the interconnect between the FPGAs. The compiler program accesses data representing the DUT's circuits, the DUT's speed constraints, and the available FPGA resources in order to partition the design transparently from the perspective of the DUT designer. Compiling an FPGA may thus be quite time consuming, for example, taking many hours, which may create schedule delays for making even minor changes during design.